This invention is generally related to ring oscillators (RO) and, more particularly, to an RO that allows parallel stressing of MOSFET devices in each of its inverter stages under any set of DC or AC voltage bias conditions.
In recent years, the information technology industry has experienced an extremely rapid growth thanks to the availability in the market of semiconductor chips with larger density, higher performance and more complex chip functions availability. One of the main contributors to this growth is the recent advance in deep sub-micron CMOS technology development. To meet the requirements of high performance microprocessors (i.e., 1 Ghz and above), the storage capacity of advanced DRAMs (1 Gbit and above) as well as the large function complexity of chips such as EDRAM or SOC, there is a need for more aggressive CMOS transistor devices. New NMOSFET and PMOSFET features have been introduced at a very fast rate. MOSFETs having a very thin gate oxide and different gate oxide processes such as nitride or deuterate oxides have been implemented. Aggressive shallow junction drain engineering such as LDD, extension and halo implants have helped to reduce the short channel effects that otherwise will be experienced, which may limit the use of deep sub-micron MOSFETs (less than 0.1 um).
An important element affecting the applicability of a given sub-micron CMOS technology to the aforementioned chip requirements is its level of reliability. In particular, it is considered critical to ensure that fundamental MOSFET device wear-out mechanisms such as hot carrier (HC) or negative bias temperature instability (NBTI) are not a limiting factor when shrinking the transistor size. This concern has prompted, among others, a big effort in technology reliability to carefully quantify the tradeoff between chip performance and MOSFET device reliability. Special focus has been given to better evaluate the link between the results of the device reliability DC stresses, typically run during the technology qualification activities and the expected end of life chip performance degradation due to the activation of possible MOSFET wear-out mechanisms. The need of reducing the technology qualification cycles to meet aggressive market demands has also forced the introduction of wafer level reliability (WLR) methodologies, mainly to quickly characterize these MOSFET reliability failure mechanisms providing the same level of confidence as in standard technologies qualification methodologies.
Conventional Ring Oscillators (RO) are simple circuits formed by an odd prime number of CMOS inverters connected in cascade to form a loop. The odd prime number of inverters in series allows the output signal of the RO to oscillate (xe2x80x9cringxe2x80x9d) between the power supply rail Vdd and the ground rail Vcc. Each inventor consists of two enhancement-mode MOSFET transistors, respectively, a pull-down NMOSFET transistor and a pull-up PMOSFET transistor. The ringing frequency depends on the output junction/capacitance load (fan-out) of each inverter stage, as shown in the conventional RO circuit illustrated in FIG. 1. The RO frequency has been traditionally considered an effective vehicle for monitoring the dependence of the chip performance on the MOSFET design used as well as on the fan-out loading scheme simulating the output RC of the circuit.
Since the RO frequency increases with an increasing Vdd, it possible to stress a typical RO circuit by applying a sufficiently large Vdd. At high Vdd bias conditions, the high frequency periodic oscillations will accelerate the degradation of both the NMOSFET and PMOSFET devices in each inverter stage and the subsequent degradation of the RO frequency. Several works, for example, have reported a correlation between the NMOSFET device degradation of the drain current in saturation conditions and the RO frequency degradation during RO stressing by high frequency ringing.
A challenging outcome of the MOSFET down scaling is that the aggressive MOSFET device design and process used in sub-micron technologies activate new device degradation mechanisms that were not observed in the past. This finding limits the applicability of traditional RO designs as stress vehicles to characterize the link between the required chip performance, parameterized by the RO frequency degradation, and MOSFET reliability wear-out mechanisms, investigated at DC conditions, in deep sub-micron technologies.
With standard RO designs it is only possible to measure the cumulative contribution of all possible device degradation mechanisms which are activated during an RO periodic waveform to the RO frequency degradation. Standard RO designs, in fact, make it possible to investigate the RO frequency degradation dependence on periodic RO voltage waveforms. It has been found in previous LSI CMOS technologies (0.25 um ground rule and above) that this frequency degradation was due to hot carrier worst case degradation during AC transients which correspond to a peak substrate current (Isx) condition for the NMOSFET, which damage is controlled by interface states generation, and a peak gate current (Igate) condition for the PMOSFET, which damage is controlled by electron trapping, as shown in prior art FIGS. 2 and 3. It is, however, not easy to decouple the contribution of each failure wear-out activated during the AC waveform to the RO frequency degradation.
Additionally, because all ROs generate only AC periodic waveforms, typical RO circuits do not allow to quantify and isolate the impact to the RO frequency degradation from other possible device degradation mechanisms, that are not activated by periodic voltage waveforms, but which are possible contributors to the performance degradation in real circuits.
A simple example of this situation is shown by the circuit described in FIG. 4. The circuit consists of an inverter stage (ISB) consisting of a PMOSFET device (PF) and a pair of NMOSFET devices (NF and NF1) in series. The gate of the NF1 device is set to Vg=Vdd to ensure that this device is always on. With the input of the inverter stage (Vin) swinging between 0 and Vdd, its output (Vout) follows between Vdd and 0. Node C will swing between 0 and Voutxe2x88x92Vth(NF1), wherein Vth(NF1) is the Vth of the NF1 device. Under these conditions the maximum Vds(NF) across NF is Vddxe2x88x92Vth(NF1), while its maximum Vgs(NF) is Vdd.
The condition Vgs(NF)  greater than Vds(NF) is possible in this situation, but it is not possible in the simple inverter scheme (IS) depicted in FIG. 5. In the case shown, Vgs(NF) is always smaller or equal to Vdd. Because of the different relationship of Vgs(NF) relative to Vds(NS) for each of these inverters, the NMOSFET (NF) device in each inverter is expected to be sensitive to different degradation mechanisms. The NF device of the simple invert circuit (IS) is only sensitive to the interface states generation damage with Vgs=@ peak lsx (FIG. 5), while the same device in the inverter circuit in FIG. 4 (ISB) is sensitive to interface states generation with Vgs at peak Isx and electron trapping at Vgs(NF)  greater than Vds(NF). The former damage produces channel mobility degradation, while the latter parasitic drain series resistance increases, as described in the article by S. K. Manhas et al, xe2x80x9cEarly stage hot carrier degradation of state of art Iss NMOSFETsxe2x80x9d, IPRS 2000.
The frequency degradation of an RO consisting of cascaded inverter stages (IS) is controlled by the interface states generation damage taking place in NMSOFET device during the RO xe2x80x9cringingxe2x80x9d, while the frequency degradation of an RO consisting of inverter stages (ISB) will have contributions from both the interface states generation as well as electron trapping. In the latter circuit, it is not possible to decouple the contribution of each mechanism to the RO frequency degradation. Therefore, it is not easy to quantify the individual contribution of each mechanism to the RO degradation. Thus, this illustrates an actual real circuit performance degradation that cannot be detected by standard RO stressing with inverter stages such as IS.
The previously described situation becomes even more complex in sub-micron CMOS technologies. New CMOS device degradation mechanisms such as negative bias temperature instabilities (NBTI), as described by G. La Rosa et al., xe2x80x9cNBTI channel hot carrier effects in PMOSFETs in advances CMOS technologiesxe2x80x9d, published by IPRS 1997, it is known that non-conducting/standby effects, electron trapping/hole injection in NMOSFETs or interface state generation in PMOSFETs, which are described by R. Woltjer et al. in an article entitled xe2x80x9cNew hot carrier degradation mechanisms in 0.25 xcexcms. PMOSFETsxe2x80x9d, 1994 Symposium on VLSI Technology; electron to electron scattering, described by S. Rauch et al., in the article entitled xe2x80x9cImpact of E.E scattering to the hot carrier degradation of deep sub-micron NMOSFETsxe2x80x9d, EDL, Vol 19, No. 12, December 1998; as well as secondary impact ionization during conductive channel hot carrier, described by B. Marchand et al, xe2x80x9cGeneration of hot carriers by secondary impact ionization in deep sub-micron devices: model and light emission characteristicsxe2x80x9d, IPRS 2000. All of these have been observed recently in DC reliability investigations of deep sub-micron CMOS technologies and are considered strong contributors to circuit performance degradation in real circuit operations.
Although these mechanisms may not be fully activated during a typical RO stressing, they may produce a strong impact in specific circuits, such as world line drivers, off-chip drivers, and the like. In this case it becomes important to carefully monitor the device degradation mechanism during the RO frequency degradation aging, in order to establish a one to one correlation between a particular MOSFET degradation mechanism and the RO frequency degradation, known as a figure of merit of the circuit performance.
Another drawback of the use of standard RO designs is that measurable frequency shifts during periodic RO AC stresses require very long term stresses. This effect is the result of the very small duty cycles associated with the transients during which the device damage is assumed to take place. Because of long stress times (100-1000 hours), RO investigations of the reliability at wafer level (WLR) are very difficult to implement. A possible use of standard RO circuits to quantify in-line monitoring of the impact of hot carrier enhancing manufacturing processes to the RO frequency degradation is typically unrealistic. Due to the very small duty cycles, RO stressing is normally carried out at package level to allow a long term stress and to measure significant RO frequency shifts.
The prior art in the field of using ring oscillator circuits to evaluate the AC reliability of a given chip basically relies on techniques to increase the RO frequency to force an AC periodic waveform to accelerate reliability failure mechanisms at burn-in and WLR conditions. This approach is the subject of several patents, e.g.:
U.S. Pat. No. 5,625,288, which describes an on-chip RO which frequency is controlled by a DC off-chip signal to stress special test structures that are used to provide information on a variety of reliability failure modes in WLR investigations. U.S. Pat. Nos. 5,995,428 and 5,457,400 which use ROs as part of burn-in stress circuits that allow the reduction of reliability defects by wafer level bum-in.
U.S. Pat. No. 5,341,096, wherein RO circuits are part of self-contained scan circuits to implement dynamic bum-in on LSI chips.
Several patents actually use ROs as monitors of in-line process variations that determine reliability fails in the field. By way of example:
U.S. Pat. No. 5,818,215 provides an RO containing a critical path of a semiconductor chip. Since the RO frequency is sensitive to process variations, the speed of the semiconductor chips under test can be investigated.
U.S. Pat. No. 5,095,267 provides an RO in a process monitor circuit to characterize the AC chip performance by DC measurements.
It is another object of Accordingly, is an object of the present invention to provide an RO circuit which frequency degradation can be induced by MOSFET device reliability wear-out mechanisms activated by an externally applied DC or AC voltage, and not limited to on-chip generated periodic RO waveforms. the present invention to provide a Ring Oscillator design to determine the dependence of the degradation of the RO frequency. (This is a typical measure of CMOS circuit performance on any possible DC MOSFET device degradation mechanism, that can be experienced by PMOSFET and NMOSFET devices in a real circuit operation using advanced sub-micron CMOS technologies).
It is a further object of the invention to provide an RO circuit, which frequency degradation is attained by parallel DC voltage biasing of each NMOSFET or PMOSFET device in each inverter stage of the RO. This biasing scheme is accomplished by appropriate parallel activation of an array of pass-gates in each inverter stage, by which any possible voltage bias is applied to the MOSFET of interest. Using this RO, it is possible to correlate the RO frequency degradation to a given device degradation mechanism (electron/hole injection, interface states generation, NBTI etc.), including those that are not typically activated by typical on-chip generated RO AC periodic waveforms.
It is another object of the present invention to provide a Ring Oscillator design which allows parallel stressing of a given MOSFET type device in each of its inverter stages at any off-chip applied AC voltage signal of interest. This RO circuit can be used to quantify the correlation between a particular externally applied AC waveform and the RO frequency degradation. In this manner, it is possible to evaluate the impact to the performance degradation of critical circuits in a chip of a specific applied AC waveform which may be experienced during real operations.
It is still another object of this invention to provide a Ring Oscillator circuit with an inverter stage (IS-Y in FIG. 5) wherein both the NMOSFET and PMOSFET devices can be directly probed for DC testing to monitor the degradation of key device parameters (such as the drain current, the threshold voltage etc.) during the frequency degradation of the RO induced by the externally applied DC or AC stress conditions.
It is a yet a further object of the present invention to provide a RO circuit which provides in-line monitoring of processes, and MOSFET device design options that are sensitive to a specific device failure mechanism and quantify their impact to the RO frequency degradation. Worst case DC voltage bias short term stresses (less then 10 sec) can be run in an in-line WLR approach to significantly degrade a given MOSFET in each inverter stage of the RO, producing sufficiently large frequency degradation of the RO in a reasonable short time to justify the use of this RO circuit for in-line monitoring.
In one aspect of the invention, there is provided an on-chip set of pass gates, controlled by appropriate off-chip DC voltage signals, to allow parallel DC stressing, as well as forcing an off-chip AC voltage waveform to a given MOSFET type device (either PMOSFET or NMOSFET) in every inverter stage of the RO. The RO circuit of the present invention is used to investigate the effect on the RO frequency degradation of any MOSFET DC degradation mechanism of interest, as well as the effect of AC voltage waveforms known to be representative of a critical circuit operation. The dependence of the RO frequency on the device degradation mechanisms activated during a critical circuit operation can be carefully investigated and quantified. This RO circuit provides an important tool in establishing a tradeoff between aggressive circuit design, device design optimization and MOSFET device reliability. A correlation between the RO frequency degradation and both PMOSFET and NMOSFET device DC parameters can be easily established.
The RO circuit can be integrated in any wafer level reliability (WLR) scheme to estimate the dependence of the RO frequency degradation in a MOSFET device to a worst case DC degradation. As such, it can be used as an in-line monitor of the performance degradation sensitivity of a given device design or CMOS process to a worst case circuit sensitive device reliability degradation mechanism.
In a second aspect of the invention, there is provided a method of determining the effect of the degradation of MOSFET on the frequency of a Ring Oscillator (RO) consisting of an odd prime number of inverter stages, each of the inverters stages having an NMOS and a PMOS field-effect transistor, the method including the steps of: a) selecting one inverter from the inverter stages of the RO, the selected inverter having testable nodes, the testable nodes being connected to inputs and outputs of the NMOS and a PMOS field-effect transistors forming the selected inverter; b) simultaneously stressing under a set of stress conditions 1) all of the NMOS FETs of each of the inverter stages, 2) all of the PMOS field-effect transistors and 3) all of the NMOS and PMOS FETs in the RO; c) measuring a shift in selected device parameters in the selected inverter; d) measuring a frequency degradation of the entire RO; and e) establishing a relationship between the shift in the device parameters and the frequency degradation and relating the relationship to a known degradation mechanism.
In a third aspect of the invention there is provided a method of determining during wafer level stressing and testing, the effect of the degradation of MOSFET on the frequency Oscillator (RO) consisting of an odd prime number of inverter stages, each of the inverters stages having an NMOS and a PMOS field-effect transistor, the method including the steps of: a) selecting one inverter from the inverter stages of the RO, the selected inverter having testable nodes, the testable nodes being connected to inputs and outputs of the NMOS and a PMOS field-effect transistors forming the selected inverter; b) simultaneously stressing under a set of stress conditions 1) all of the NMOS FETs of each of the inverter stages, 2) all of the PMOS field-effect transistors and 3) all of the NMOS and PMOS FETs in the RO; c) measuring a shift in selected device parameters in the selected inverter; d) measuring a frequency degradation of the entire RO; and e) establishing a relationship between the shift in the device parameters and the frequency degradation and relating the relationship to a known degradation mechanism, wherein stressing and testing of the wafer is performed under accelerated stress conditions to meet a predetermined device reliability target.